Consult their Glossary Entries for Details

The default serial routines used by the onboard kernel assume that full duplex communications are available, so you cannot use the RS485 protocol to program the controller. RS485 is another protocol supported by the primary serial port on the QVGA Controller. By polling the Port A pin or by setting up an interrupt service routine, you can configure the QScreen to ignore the SCK input when /SS is high and keep MISO in a high-impedance state so that it does not interfere with the SPI bus. If the 68HC11 is initialized as a master by setting the MSTR bit, then bit 5 of the Port D data direction register (PORTD.DIRECTION) determines whether /SS is an input or an output. A three-post jumper located between the third socket and H6 configures the primary serial port for either RS232 or RS485 operation. A jumper, J3, configures the primary serial port for either RS232 or RS485 operation. We can gain insight into the operation of the RS232 protocol by examining the signal connections used for the primary serial port in Table 11 5. The transmit and receive data signals carry the messages being communicated between the QVGA Controller and the PC or terminal.

Likewise, the terminal’s transmit signal TxD is connected to the QVGA Controller’s receive signal RxD1. To provide a convenient means of attaching two grounds to the serial cable, there are several pins (labeled DGND) on the communications connector that are connected to the controller’s ground plane. For RS485 operation: Install the jumper shunt across the two pins closest to the J3 silk screen. An RS485 transceiver is present on the QVGA Controller, and its data direction is controlled by pin 4 of port PPC of the peripheral interface adapter (PIA). In a place where you are hindered by the electrically noisy environment, RS485 will be the optimal choice. The QVGA Controller offers a unique addition to full duplex RS232: it can place its RS232 transmitter into a high impedance silent mode under software control. For RS232 operation: Install the jumper shunt across the two pins closest to the crystal (the default configuration).

While the default baud rate of the primary serial port is 9600 baud, you can speed your communications and download times appreciably by switching to a faster baud rate. It is supported by virtually all personal computers, and is the default protocol for both of the QVGA Controller’s serial ports. Most computers conform to IBM PC AT-compatible RS232 interfaces which use 9-pin D-Type connectors, consequently the QVGA Controller brings out its serial ports to two female 9-pin D-Type connectors. RS232 is by far the most common protocol. Connecting a standard full duplex link RS232 between two computers is the same as with a standard RS232 link, with the TxD (transmitter output) of each computer connected to the RxD (receiver input) of the other computer. By connecting pairs of these handshaking signals together, the terminal or PC can be made to think that the QVGA Controller is always ready to send and receive data. It provides a convenient means of connecting the QVGA Controller to a variety of peripheral devices, including analog to digital and digital to analog converters, real time clocks, and other computers which use high speed communication. The interface can be used to support analog to digital and digital to analog converters, networks of many computers controlled by a single master, or networks of devices controlled by several coordinated masters.

This allows you to configure full duplex multi-drop networks in which a single master can sequentially address one of many slaves and start a full-duplex exchange of data. For example, at 4800 baud (bits per second), each bit lasts about 200 microseconds (µs), and if communications are full duplex (e.g., if the QVGA Controller echoes each incoming character), then there is a serial interrupt every 100 µs or so. For example, at 4800 baud (bits per second), each bit lasts about 200 microseconds (µs), and if communications are full duplex (e.g., if the QScreen Controller echoes each incoming character), then there is a serial interrupt every 100 µs or so. The SPIE bit in the SPCR (SPI control register) enables SPI interrupt handling. Consult the data sheets for any peripheral devices that you are interfacing to the SPI and, if a different configuration is needed, follow the instructions below to set up the appropriate SPI data transfer protocol. A mode fault occurs when the SPI senses that a multimaster conflict (MC68HC11F1 Technical Data Manual, p.10-5) exists on the network as explained above in connection with the /SS input. When it is low, the transceiver is in receive mode.

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